ECE 495 - Computer Engineering Design Laboratory

• Appendix 2.1
• Appendix 4.1
• Appendix 7.1
• Appendix 7.2

# Appendix 2.1

## Part 1

-- ECE 495 - Experiment 2, part 1
library IEEE;
use IEEE.std_logic_1164.all;

ENTITY part1 IS

PORT(X, Y:       IN STD_LOGIC_VECTOR(7 downto 0);
M:             OUT STD_LOGIC_VECTOR (7 downto 0);
sel:     IN STD_LOGIC);

END part1;

ARCHITECTURE apart1 OF part1 IS
BEGIN
-- generate function for each spot in our 8-element vector
M_G: for i in 7 downto 0 generate
-- function to multiplex the two inputs
M(i) <= (NOT sel AND X(i)) or (sel AND Y(i));
end generate;
end apart1;

## Part 2

library IEEE;
use IEEE.std_logic_1164.all;
ENTITY part2 IS
PORT(sel, U, V, W, X, Y: IN STD_LOGIC_VECTOR(2 downto 0);
M: OUT STD_LOGIC_VECTOR (2 downto 0));
END part2;
ARCHITECTURE apart2 OF part2 IS

-- need signals for 3 outputs (one from each mux)
SIGNAL mux1, mux2, mux3: STD_LOGIC_VECTOR(2 downto 0);
BEGIN
-- generate the output signals for each of the muxes
mux1_G: for i in 2 downto 0 generate
mux1(i) <= (NOT sel(0) AND U(i)) or (sel(0) AND V(i));
end generate;
mux2_G: for i in 2 downto 0 generate
mux2(i) <= (NOT sel(0) AND W(i)) or (sel(0) AND X(i));
end generate;
mux3_G: for i in 2 downto 0 generate
mux3(i) <= (NOT sel(1) AND mux1(i)) or (sel(1) AND
mux2(i));
end generate;
M_G: for i in 2 downto 0 generate
M(i) <= (NOT sel(2) AND mux3(i)) or (sel(2) AND Y(i));
end generate;
END apart2;

# Appendix 4.1

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_ARITH.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;

ENTITY lcd_disp IS

PORT(reset, clk:                     IN STD_LOGIC;
LCD_RS, LCD_EN, LCD_ON:      OUT STD_LOGIC;
LCD_RW:                      BUFFER STD_LOGIC;
LCD_DATA:                    INOUT STD_LOGIC_VECTOR(7 downto 0));
END lcd_disp;

ARCHITECTURE alcd_disp OF lcd_disp IS

TYPE states IS (hold, func_set, display_on, mode_set, write_char1,
write_char2, write_char3, write_char4, write_char5,
write_char6, write_char7, write_char8, write_char9,
write_char10, write_char11, write_char12,
return_home,
toggle_e, reset1, reset2, reset3, display_off,
display_clear);
SIGNAL state, next_command: states;
SIGNAL data_bus: STD_LOGIC_VECTOR(7 downto 0);
SIGNAL clk_count_400Hz: STD_LOGIC_VECTOR(19 downto 0);
SIGNAL clk_400Hz: STD_LOGIC;
SIGNAL char1_data, char2_data: STD_LOGIC_VECTOR(7 downto 0);
BEGIN
LCD_ON <= '1';

-- bidirectional tri-state LCD data bus
LCD_DATA <= data_bus WHEN LCD_RW = '0' ELSE "ZZZZZZZZ";

PROCESS
BEGIN
-- must slow down clock to 400Hz for LCD use
WAIT UNTIL rising_edge(clk);
IF reset = '0' THEN
clk_count_400Hz <= X"00000";
clk_400Hz <= '0';
ELSE
IF clk_count_400Hz < X"0F424" THEN
clk_count_400Hz <= clk_count_400Hz + 1;
ELSE
clk_count_400Hz <= X"00000";
clk_400Hz <= NOT clk_400Hz;
END IF;
END IF;
END PROCESS;

PROCESS (clk_400Hz, reset)
BEGIN
IF reset = '0' THEN
state <= reset1;
data_bus <= X"38";
next_command <= reset2;
LCD_EN <= '1';
LCD_RS <= '0';
LCD_RW <= '0';
ELSIF rising_edge(clk_400Hz) THEN
CASE state IS
-- Set Function to 8-bit transfer and 2 line display with 5x8 Font size
-- see Hitachi HD44780 family data sheet for LCD command and timing details
WHEN reset1 =>
LCD_EN <= '1';
LCD_RS <= '0';
LCD_RW <= '0';
data_bus <= X"34";
state <= toggle_e;
next_command <= reset2;
WHEN reset2 =>
LCD_EN <= '1';
LCD_RS <= '0';
LCD_RW <= '0';
data_bus <= X"34";
state <= toggle_e;
next_command <= reset3;
WHEN reset3 =>
LCD_EN <= '1';
LCD_RS <= '0';
LCD_RW <= '0';
data_bus <= X"38";
state <= toggle_e;
next_command <= func_set;
-- states above needed for pushbutton reset of LCD display
WHEN func_set =>
LCD_EN <= '1';
LCD_RS <= '0';
LCD_RW <= '0';
data_bus <= X"34";
state <= toggle_e;
next_command <= display_off;
-- turn off display and turn off cursor
WHEN display_off =>
LCD_EN <= '1';
LCD_RS <= '0';
LCD_RW <= '0';
data_bus <= X"08";
state <= toggle_e;
next_command <= display_clear;
-- turn on display and turn off cursor
WHEN display_clear =>
LCD_EN <= '1';
LCD_RS <= '0';
LCD_RW <= '0';
data_bus <= X"01";
state <= toggle_e;
next_command <= display_on;
-- turn on display and turn off cursor
WHEN display_on =>
LCD_EN <= '1';
LCD_RS <= '0';
LCD_RW <= '0';
data_bus <= X"0C";
state <= toggle_e;
next_command <= mode_set;
-- set write mode to auto increment address and move cursor to the right
WHEN mode_set =>
LCD_EN <= '1';
LCD_RS <= '0';
LCD_RW <= '0';
data_bus <= X"06";
state <= toggle_e;
next_command <= write_char1;
-- write hex character in first LCD character location
WHEN write_char1 =>
LCD_EN <= '1';
LCD_RS <= '1';
LCD_RW <= '0';
data_bus <= X"48"; -- H
state <= toggle_e;
next_command <= write_char2;
-- write hex character in second LCD character location
WHEN write_char2 =>
LCD_EN <= '1';
LCD_RS <= '1';
LCD_RW <= '0';
data_bus <= X"45"; -- E
state <= toggle_e;
next_command <= write_char3;
-- write hex character in third LCD character location
WHEN write_char3 =>
LCD_EN <= '1';
LCD_RS <= '1';
LCD_RW <= '0';
data_bus <= X"4C"; -- L
state <= toggle_e;
next_command <= write_char4;
-- write hex character in fourth LCD character location
WHEN write_char4 =>
LCD_EN <= '1';
LCD_RS <= '1';
LCD_RW <= '0';
data_bus <= X"4C"; -- L
state <= toggle_e;
next_command <= write_char5;
-- write hex character in fifth LCD character location
WHEN write_char5 =>
LCD_EN <= '1';
LCD_RS <= '1';
LCD_RW <= '0';
data_bus <= X"4F"; -- O
state <= toggle_e;
next_command <= write_char6;
-- write hex character in sixth LCD character location
WHEN write_char6 =>
LCD_EN <= '1';
LCD_RS <= '1';
LCD_RW <= '0';
data_bus <= X"20"; -- space
state <= toggle_e;
next_command <= write_char7;
-- write hex character in seventh LCD character location
WHEN write_char7 =>
LCD_EN <= '1';
LCD_RS <= '1';
LCD_RW <= '0';
data_bus <= X"57"; -- W
state <= toggle_e;
next_command <= write_char8;
-- write hex character in eighth LCD character location
WHEN write_char8 =>
LCD_EN <= '1';
LCD_RS <= '1';
LCD_RW <= '0';
data_bus <= X"4F"; -- O
state <= toggle_e;
next_command <= write_char9;
-- write hex character in nineth LCD character location
WHEN write_char9 =>
LCD_EN <= '1';
LCD_RS <= '1';
LCD_RW <= '0';
data_bus <= X"52"; -- R
state <= toggle_e;
next_command <= write_char10;
-- write hex character in tenth LCD character location
WHEN write_char10 =>
LCD_EN <= '1';
LCD_RS <= '1';
LCD_RW <= '0';
data_bus <= X"4C"; -- L
state <= toggle_e;
next_command <= write_char11;
-- write hex character in eleventh LCD character location
WHEN write_char11 =>
LCD_EN <= '1';
LCD_RS <= '1';
LCD_RW <= '0';
data_bus <= X"44"; -- D
state <= toggle_e;
next_command <= write_char12;
-- write hex character in twelveth LCD character location
WHEN write_char12 =>
LCD_EN <= '1';
LCD_RS <= '1';
LCD_RW <= '0';
data_bus <= X"21"; -- !
state <= toggle_e;
next_command <= return_home;
-- Return write address to first character postion
WHEN return_home =>
LCD_EN <= '1';
LCD_RS <= '0';
LCD_RW <= '0';
data_bus <= X"80";
state <= toggle_e;
next_command <= write_char1;
-- The next two states occur at the end of each command to the LCD
-- Toggle E line - falling edge loads inst/data to LCD controller
WHEN toggle_e =>
LCD_EN <= '0';
state <= hold;
-- Hold LCD inst/data valid after falling edge of E line

WHEN hold =>
state <= next_command;
END CASE;
END IF;
END PROCESS;
END alcd_disp;

# Appendix 7.1

VHDL code for exp7_alu

-- CoE 485 Exp. 7
-- 8-bit ALU
-- Dr. Hou
--
-- result <= a + b, if op = 0
--        <= a and b, if op = 1
--
library ieee;
use ieee.std_logic_1164.all;
library lpm;
use lpm.lpm_components.all;

entity exp7_alu is
port (a, b: in std_logic_vector(7 downto 0);

op: in std_logic_vector(0 downto 0);
result: out std_logic_vector(7 downto 0));

end exp7_alu;

architecture structural of exp7_alu is
signal add_result, and_result: std_logic_vector(7 downto 0);
signal mux_data: std_logic_2D(1 downto 0, 7 downto 0);
begin

generic map (lpm_width=>8)

and_result <= a and b;
for_label: for i in 7 downto 0 generate

mux_data(1,i) <= and_result(i);

end generate;
alu_mux: lpm_mux

generic map (lpm_width=>8, lpm_size=>2, lpm_widths=>1)
port map (data=>mux_data, result=>result, sel=>op);

end structural;

# Appendix 7.2

## VHDL code for exp7_useq

-- CoE 485 Exp. 7
-- uSequencer
-- Dr. Hou
--
library ieee;
use ieee.std_logic_1164.all;
library lpm;
use lpm.lpm_components.all;

entity exp7_useq is

generic (uROM_width: integer := 25;

uROM_file: string := "");

port (opcode: in std_logic_vector(3 downto 0);

uop: out std_logic_vector(1 to (uROM_width-9));
enable, clear: in std_logic;
clock: in std_logic);

end exp7_useq;

architecture structural of exp7_useq is

signal uROM_address: std_logic_vector (7 downto 0);
signal uROM_out: std_logic_vector (uROM_width-1 downto 0);
signal uPC_mux_data: std_logic_2D(1 downto 0, 7 downto 0);
signal uPC_mux_sel: std_logic_vector(0 to 0);
signal uPC_mux_out: std_logic_vector(7 downto 0);
signal temp: std_logic_vector(7 downto 0);
begin

temp <= opcode & "0000";
for_label: for i in 0 to 7 generate

uPC_mux_data(0, i) <= uROM_out(i);
uPC_mux_data(1, i) <= temp(i);

end generate;
uPC_mux_sel(0) <= uROM_out(8);
uPC_mux: lpm_mux

generic map (lpm_width=>8, lpm_size=>2, lpm_widths=>1)
port map (result=>uPC_mux_out, data=>uPC_mux_data, sel=>uPC_mux_sel);

uPC: lpm_ff

generic map (lpm_width=>8)