ECE Undergraduate Laboratories
ECE 459 - Advanced Computer System Design Laboratory

Experiment 3: Systolic-Array Implementation of Matrix-By-Matrix Multip lication

NOTES: Simulation of the design will be done in Modelsim Altera.
Hardware implementation of the algorithm will be done on the DE2 Altera board.

Systolic-Array Implementation

Systolic-Array Implementation

Architecture of the entire system

The system should have the following components:
-  A Systolic-Array of execute-processors circuit.
-  A value generator circuit. This circuit will sequentially produce and push new input values into the rows and columns of the Systolic-Array..
-  An Output-Handler circuit. The purpose of this circuit is to output outside the results of matrix multiplication. You can either choose to display the results on LEDs or on an LCD Module.
-  A controller to properly control the execution of all of the above circuits.
Val Generator

Extra-credit for:

- Building a Systolic Array for input matrices of size 4 x 4 containing more than onebit integer elements;
- Building an original Out Handler circuit.

Useful Links

  1. Altera DE 2 board tutorial

  2. Altera DE2 User Manual

  3. Altera DE 2 board resources

  4. VHDL manual