Experiment 3: Systolic-Array Implementation of Matrix-By-Matrix Multip lication
HELP NOTES
NOTES: Simulation of the design will be done in Modelsim Altera.
Hardware implementation of the algorithm will be done on the DE2 Altera board.
Systolic-Array Implementation
Architecture of the entire system
The system should have the following components:
- A Systolic-Array of execute-processors circuit.
- A value generator circuit. This circuit will sequentially produce and push new input values into the rows and columns of the Systolic-Array..
- An Output-Handler circuit. The purpose of this circuit is to output outside the results of matrix multiplication. You can either choose to display the results on LEDs or on an LCD Module.
- A controller to properly control the execution of all of the above circuits.
Extra-credit for:
- Building a Systolic Array for input matrices of size 4 x 4 containing more than onebit integer elements;
- Building an original Out Handler circuit.
Useful Links
- Altera DE 2 board tutorial
ftp://ftp.altera.com/up/pub/Tutorials/DE2/Digital_Logic/tut_quartus_intro_vhdl.pdf - Altera DE2 User Manual
ftp://ftp.altera.com/up/pub/Webdocs/DE2_UserManual.pdf - Altera DE 2 board resources
http://users.ece.gatech.edu/~hamblen/DE2/ - VHDL manual
http://www.usna.edu/EE/ee462/MANUALS/vhdl_ref.pdf
http://www.cse.unsw.edu.au/~cs3211/refs/vhdl1.pdf
http://home.dei.polimi.it/sami/VHDL_reference_manual.pdf